Quartus® Prime Pro Edition User Guide: Programmer

ID 683039
Date 7/07/2025
Public
Document Table of Contents

1.6. Generating Programming Files for Altera® FPGA Devices with Hard Processor Systems

When generating programming files for Altera® FPGA devices with a Hard Processor System (HPS), you must first determine what boot flow you want to use for the device: HPS Boot First or FPGA Configuration First.

Note: You must assign all I/Os in your design before you can generate a .sof file for programming the target device. Starting in Quartus® Prime Pro Edition version 25.1.1, the Assembler does not generate a .sof programming file during compilation unless all I/Os have location and I/O standard assignments. Previously, Quartus® Prime Pro Edition only issued a critical warning during the Fitter stage if a design lacks complete pin location and I/O standard assignments but still allowed .sof generation.

Depending on the boot flow that you want to use, follow the instructions in one of the following sections.