Quartus® Prime Pro Edition User Guide: Programmer

ID 683039
Date 4/01/2024
Document Table of Contents Configuration Modes (Convert Programming Files)

Select one of the following Configuration modes in Convert Programming Files for generation of secondary programming files:
Table 5.  Convert Programming Files Configuration Modes
Programming Mode Description
1-Bit/2-Bit/4-Bit/8-Bit Passive Serial An external controller passes configuration data to one or more FPGA devices via a serial data stream. The FPGA device is a slave device with a 5-wire interface to the external controller. The external controller can be an intelligent host such as a microcontroller or CPU, or the Quartus® Prime Programmer, or an EPC2 or EPC16 configuration device.
Active Parallel Supports configuration devices using commodity 16-bit parallel flash memories to control the configuration interface.
Active Serial For storing configuration data in a low-cost serial configuration device with non-volatile memory. Serial configuration devices provide a serial interface to access the configuration data. During device configuration, the device reads the configuration data through the serial interface, decompresses the data if necessary, and configures their SRAM cells.
Active Serial x4
AVST x8/x16/x32 The Avalon® streaming configuration mode uses an external host, such as a microprocessor or MAX® 10 device. The external host controls the transfer of configuration data from an external storage such as flash memory to the FPGA. The design that controls the configuration process resides in the external host. You can use the PFL II IP core with an MAX® 10 device as the host to read configuration data from a flash memory device that configures an FPGA.
Passive Parallel Synchronous An external controller, such as a CPU, loads the design data into a device via a common data bus. Data is latched by the device on the first rising edge of a CPU-driven clock signal. The next eight falling clock edges serialize this latched data within the device. The device latches the next 8-bit byte of data on every eighth rising edge of the clock signal until the device is completely configured.
Passive Parallel Asynchronous An external controller, such as a CPU, loads the design data into a device via a common data bus. The device accepts a parallel byte of input data. Intelligent communication between the external controller and the device allows the external controller to configure the device.
Internal Configuration Uses a .pof file for internal configuration of the MAX® 10 device’s Configuration Flash Memory (CFM) and User Flash Memory (UFM) via a download cable Quartus® Prime Programmer.