Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

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ID 683038
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. Design Example Description x
1.1. Functional Description for the Programmed Input/Output (PIO) Design Example 1.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Testbench
2.3.1. Testbench x
2.3.1.1. Test Driver Module 2.3.1.2. PIO Design Example Testbench 2.3.1.3. SR-IOV Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example
1. Design Example Description
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

2.3.1.1. Test Driver Module

The test driver module, intel_pcie_ptile_tbed_hwtcl.v, instantiates the top-level BFM,altpcietb_bfm_top_rp.v.

The top-level BFM completes the following tasks:

  1. Instantiates the driver and monitor.
  2. Instantiates the Root Port BFM.
  3. Instantiates the serial interface.

The configuration module, altpcietb_g3bfm_configure.v, performs the following tasks:

  1. Configures and assigns the BARs.
  2. Configures the Root Port and Endpoint.
  3. Displays comprehensive Configuration Space, BAR, MSI, MSI-X, and AER settings.
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