Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

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ID 683038
Date 10/04/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. Design Example Description x
1.1. Functional Description for the Programmed Input/Output (PIO) Design Example 1.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Testbench
2.3.1. Testbench x
2.3.1.1. Test Driver Module 2.3.1.2. PIO Design Example Testbench 2.3.1.3. SR-IOV Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example
1. Design Example Description
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.10.04 21.3 6.0.0

Changed the supported configurations for the SR-IOV design example from Gen3 x16 EP and Gen4 x16 EP to Gen3 x8 EP and Gen4 x8 EP in the Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example section.

Added the support for the Intel® Stratix® 10 DX P-tile Production FPGA Development Kit to the Generating the Design Example section.

2021.07.01 21.2 5.0.0

Removed the simulation waveforms for the PIO and SR-IOV design examples from the section Simulating the Design Example.

Updated the command to display the BDF in the section Running the PIO Design Example.

2020.10.05 20.3 3.1.0 Removed the Registers section since the Avalon Streaming design examples have no control register.
2020.07.10 20.2 3.0.0

Added simulation waveforms, test case descriptions and test result descriptions for the design examples.

Added simulation instructions for the ModelSim simulator to the Simulating the Design Example section.

2020.05.07 20.1 2.0.0

Updated the document title to Intel FPGA P-Tile Avalon® streaming IP for PCI Express* Design Example User Guide to meet new legal naming guidelines.

Updated the VCS interactive mode simulation command.
2019.12.16 19.4 1.1.0 Added SR-IOV design example description.
2019.11.13 19.3 1.0.0 Added Gen4 x8 Endpoint and Gen3 x8 Endpoint to the list of supported configurations.
2019.05.03 19.1.1 1.0.0 Initial release.
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