Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

ID 767849
Date 3/31/2023
Public

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Optimization Flags

The following table lists OpenCL optimization flags and their equivalents in SYCL*:

OpenCL SYCL Description
-clock=<clock_target> -Xsclock=<clock_target>

Determines the pipelining effort the scheduler attempts during the scheduling process.

-no-interleaving=<global_memory_type> -Xsno-interleaving=<global_memory_type>

Disables burst-interleaving for all global memory banks of the same type and manages them manually.

-global-ring -Xsglobal-ring

Overrides compiler's choice of optimal global memory interconnect topology (based on various design characteristics) and forces a ring topology.

-force-single-store-ring -Xsforce-single-store-ring

Narrows the interconnect to save area while limiting write-only throughput to one bank's worth.

-num-reorder -Xsnum-reorder=<N>

Narrows the interconnect to save area while reducing read-only throughput, where N is the number of bank's worth of read bandwidth you desire.