SYCL* 2020 in hipSYCL: DPC++ on AMD* and NVIDIA*

One of the four major SYCL* implementations, hipSYCL, focuses on aggregating hardware support for multivendor hardware provided by those toolchains within one single framework. Recently, hipSYCL has also started adopting DPC++ and SYCL 2020 features, such as unified shared memory, reductions, and more, to increase portability of code using these features for AMD* GPUs.

After a brief introduction to hipSYCL, this video explores how it fits into the oneAPI ecosystem, specifically SYCL 2020 and DPC++ features like unified shared memory or group algorithms across supported hardware. Learn what you can expect from hipSYCL in terms of functionality and performance.

 

Speaker

Aksel Alpay is a researcher and software engineer from Heidelberg University where he works on high-performance computing topics. In particular, he is the creator and lead developer of the hipSYCL SYCL implementation, and also engages within the Khronos SYCL working group to advance the language.

Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.