Bringing HIP to oneAPI

Derived from the University of Finland’s HIPCL, the new heterogeneous interface for portability (HIP) back end, CHIP-SPV, can target Intel® GPUs through Level Zero or OpenCL™ Runtimes. Learn how HIP is implemented on Intel GPUs and why it is important to increase the portability of the application.


Brice Videau is a computer scientist at Argonne National Laboratory's Leadership Computing Facility. His research focuses on heterogeneous programming models for HPC, performance optimization, and autotuning. Brice is also a member of the OpenCL™ software working group at Khronos*.