Pin - A Binary Instrumentation Tool

Gadi Haber Coby Tayree

A small subset of the conference publications about Pin or using Pin. The text for most of the entries below was created by going to the ACM Library, finding the paper, clicking on 'ACM Ref' and doing a cut and paste. If there is an ACM link for a reference, click through to get the full text or a bibtex reference.

For an up-to-date list of all papers citing the primary Pin paper, see Google Scholar.

2018

"Chaperone - Runtime System for Instrumenting Applications via Partial Binary Translation", SYSTOR '18: Proceedings of the 11th ACM International Systems and Storage Conference Pages 49–58.

2012

Gregory Lueck, Harish Patil, Cristiano Pereira. "PinADX: An Interface for Customizable Debugging with Dynamic Instrumentation". Proceedings of the IEEE/ACM international symposium on Code generation and optimization (CGO 2012), pages 114-123. slides. DOI.

2011

Amitabha Roy, Steven Hand, and Tim Harris. "Hybrid Binary Rewriting for Memory Access Instrumentation". Proceedings of the 7th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE '11), pages 227-238. DOI

2010

Alex Skaletsky, Tevi Devor, Nadav Chachmon, Robert Cohn, Kim Hazelwood, Vladimir Vladimirov, Moshe Bach. "Dynamic Program Analysis of Microsoft Windows Applications," International Symposium on Performance Analysis of Software and Systems (ISPASS). White Plains, NY. April 2010.
Harish Patil, Cristiano Pereira, Mack Stallcup, Gregory Lueck, James Cownie. "PinPlay: A Framework for Deterministic Replay and Reproducible Analysis of Parallel Programs". Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization (CGO 2010). CGO 2010 Best Paper Award Winner. DOI
Moshe Bach, Mark Charney, Robert Cohn, Tevi Devor, Elena Demikovsky, Kim Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, Ady Tal. "Analyzing Parallel Programs with Pin," IEEE Computer. March 2010, vol. 43, no. 3, pages 34-41.

2009

Dan Upton, Kim Hazelwood, Robert Cohn, and Greg Lueck. "Improving Instrumentation Speed via Buffering" 2009 Workshop on Binary Instrumentation and Applications (WBIA09), New York, New York, December 2009.
Alexandre Strube, Dolores Rexachs and Emilio Luque. "Software Probes: A Method for Quickly Characterizing Applications' Performance on Heterogeneous Environments". pp.262-269, 2009 International Conference on Parallel Processing Workshops, (ICPP), Vienna, Austria, September 2009.
Kim Hazelwood, Greg Lueck, and Robert Cohn. "Scalable Support for Multithreaded Applications on Dynamic Binary Instrumentation Systems," Proceedings of the 2009 International Symposium on Memory Management (ISMM). Dublin, Ireland. June 2009, pages 20-29.
Paruj Ratanaworabhan, Martin Burtscher, Darko Kirovski, Rahul Nagpal, Karthik Pattabiraman, and Benjamin Zorn, "Detecting and Tolerating Asymmetric Races", 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009), Raleigh, NC, February 2009.
Soyeon Park, Shan Lu, and Yuanyuan Zhou. "CTrigger: Exposing Atomicity Violation Bugs from Their Hiding Places" 14th International Conference on Architectural Support for Programming Languages and Operating Systems, March 2009.

2008

Danny Quist, Colin Ames, "Temporal Reverse Engineering," Blackhat USA, 2008. slides
Arkaitz Ruiz-Alvarez and Kim Hazelwood. "Evaluating the Impact of Dynamic Binary Translation Systems on Hardware Cache Performance," in Proceedings of the IEEE International Symposium on Workload Characterization (IISWC). Seattle, Washington, USA. September 2008
Alexandre Strube, Emilio Luque, Dolores Rexachs, "Software Probes: towards a quick method for machine characterization and application performance prediction", 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), Krakow, Poland, July 2008.

2007

Prashanth P. Bungale, Chi-Keung Luk, "PinOS: A Programmable Framework for Whole-System Dynamic Instrumentation," Proceedings of the 3rd ACM/USENIX International Conference on Virtual Execution Environments (VEE 2007), June 2007. PDF
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Joseph Blomstedt, Daniel A. Connors, "Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance, "International Conference on Dependable Systems and Networks (DSN), June, 2007. PDF
Tipp Moseley, Daniel A. Connors, Dirk Grunwald, Ramesh Peri. "Identifying Potential Parallelism via Loop-centric Profiling," Proceedings of the 2007 Conference on Computing Frontiers (CF), May, 2007. PDF BiBTeX
Sean Peisert, Matt Bishop, Sidney Karin, and Keith Marzullo, "Analysis of Computer Intrusions Using Sequences of Function Calls," IEEE Transactions on Dependable and Secure Computing (TDSC), 4(2), April-June 2007.
Steven Wallace and Kim Hazelwood, "SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance," International Symposium on Code Generation and Optimization (CGO), March 2007. PDF BiBTeX
Vijay Janapa Reddi, Robert Cohn, Daniel A. Connors, Michael D. Smith, "Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications," Proceedings of the 5th International Conference on Code Generation and Optimization (CGO), March, 2007. PDF
Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Dirk Grunwald, Ramesh Peri. "Shadow Profiling: Hiding Instrumentation Costs with Parallelism," Proceedings of the 5th International Conference on Code Generation and Optimization (CGO), March, 2007. PDF BiBTeX
Joseph Tucek, James Newsome, Shan Lu, Chengdu Huang, Spiros Xanthos, David Brumley, Yuanyuan Zhou, Dawn Song, Sweeper: A Lightweight End-to-End System for Defending Against Fast Worms. PDF BiBTeX In the Proceedings of the 2007 EuroSys Conference, 2007.

2006

Hazelwood, K. and Klauser, A. A dynamic binary instrumentation engine for the ARM architecture. In Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis For Embedded Systems (Seoul, Korea, October 22 - 25, 2006). 261-270. PDF BiBTeX
Lu, S., Tucek, J., Qin, F., and Zhou, Y. AVIO: detecting atomicity violations via access interleaving invariants. SIGARCH Comput. Archit. News 34, 5 (Oct. 2006), 37-48. DOI
Narayanasamy, S., Pereira, C., Patil, H., Cohn, R., and Calder, B. Automatic logging of operating system effects to guide application-level architecture simulation. In Proceedings of the Joint international Conference on Measurement and Modeling of Computer Systems (Saint Malo, France, June 26 - 30, 2006). SIGMETRICS '06/Performance '06. 216-227. DOI
Hazelwood, K. and Cohn, R. A Cross-Architectural Interface for Code Cache Manipulation. In Proceedings of the International Symposium on Code Generation and Optimization (March 26 - 29, 2006). Code Generation and Optimization. 17-27. PDF BiBTeX
Reis, G., August, D., Cohn, R., and Mukherjee, S. Software Fault Detection Using Dynamic Instrumentation. In Proceedings of the Fourth Annual Boston Area Architecture Workshop (BARC), February 2006. PDF
Isci, C., and Martonosi, M. Phase Characterization for Power: Evaluating Control-Flow-Based and Event-Counter-Based Techniques. In Proceedings of the 12th International Symposium on High-Performance Computer Architecture (HPCA-12), February 2006. PDF
Wu, Q., Martonosi, M., Clark, D. W., Vijay Janapa Reddi, Connors, D., Wu, Y., Lee, J., and Brooks, D. Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance. IEEE Micro 26, 1 (Jan. 2006), 119-129. DOI

2005

Kumar, N. and Peri, R. Transparent debugging of dynamically instrumented programs. SIGARCH Computer Architecture News 33, 5 (Dec. 2005), 57-62. DOI
Moffie, M. and Kaeli, D. ASM: application security monitor. SIGARCH Computer Architecture News 33, 5 (Dec. 2005), 21-26. DOI
McCurdy, C. and Fischer, C. Using Pin as a memory reference generator for multiprocessor simulation. SIGARCH Computer Architecture News 33, 5 (Dec. 2005), 39-44. DOI
Pan, H., Asanovic, K., Cohn, R., and Luk, C. Controlling program execution through binary instrumentation. SIGARCH Computer Architecture News 33, 5 (Dec. 2005), 45-50. DOI
Vijay Janapa Reddi, Connors, D., and Cohn, R. S. Persistence in dynamic code transformation systems. SIGARCH Computer Architecture News 33, 5 (Dec. 2005), 69-74. DOI
Srinivasan, R. and Lubeck, O. MonteSim: a Monte Carlo performance model for in-order microachitectures. SIGARCH Computer Archiecture News 33, 5 (Dec. 2005), 75-80. DOI
Kim, H., Mutlu, O., Stark, J., and Patt, Y. N. Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. In Proceedings of the 38th Annual IEEE/ACM international Symposium on Microarchitecture (Barcelona, Spain, November 12 - 16, 2005). International Symposium on Microarchitecture. 43-54. DOI
Hiniker, D., Hazelwood, K., and Smith, M. D. Improving Region Selection in Dynamic Optimization Systems. In Proceedings of the 38th Annual IEEE/ACM international Symposium on Microarchitecture (Barcelona, Spain, November 12 - 16, 2005). 141-154. DOI
Wu, Q., Martonosi, M., Clark, D. W., Vijay Janapa Reddi, Dan Connors, D., Wu, Y., Lee, J., and Brooks, D. A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. In Proceedings of the 38th Annual IEEE/ACM international Symposium on Microarchitecture (Barcelona, Spain, November 12 - 16, 2005). 271-282. DOI
Shye, A., Iyer, M., Vijay Janapa Reddi, and Connors, D. A. Code coverage testing using hardware performance monitoring support. In Proceedings of the Sixth international Symposium on Automated Analysis-Driven Debugging (Monterey, California, USA, September 19 - 21, 2005). 159-163. DOI
Luk, C., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Vijay Janapa Reddi, and Hazelwood, K. Pin: building customized program analysis tools with dynamic instrumentation. In Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation (Chicago, IL, USA, June 12 - 15, 2005). 190-200. DOI
Marathe, J., Mueller, F., and de Supinski, B. A hybrid hardware/software approach to efficiently determine cache coherence Bottlenecks. In Proceedings of the 19th Annual international Conference on Supercomputing (Cambridge, Massachusetts, June 20 - 22, 2005). 21-30. DOI
Narayanasamy, S., Pokam, G., and Calder, B. 2005. BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging. In Proceedings of the 32nd Annual international Symposium on Computer Architecture (June 04 - 08, 2005). International Symposium on Computer Architecture. IEEE Computer Society, Washington, DC, 284-295. DOI
Shye, A., Iyer, M., Moseley, T., Hodgdon, D., Fay, D., Reddi, Vijay Janapa Reddi, and Connors, D. A. Analyis of Path Profiling Information Generated with Performance Monitoring Hardware. In Proceedings of the 9th Annual Workshop on interaction between Compilers and Computer Architectures (interact'05) - Volume 00 (February 13 - 13, 2005). 34-43. DOI

2004

Patil, H., Cohn, R., Charney, M., Kapoor, R., Sun, A., and Karunanidhi, A. Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation. In Proceedings of the 37th Annual IEEE/ACM international Symposium on Microarchitecture (Portland, Oregon, December 04 - 08, 2004). 81-92. DOI

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