Introduction
Detailed Description
This application note demonstrates how to use the Quartus® Prime software System Console to access hardware modules (that is, peripherals) that are instantiated in the FPGA design. Using the design example, you can interact with the Platform Designer system through a JTAG cable connection to the Intel FPGA. You send read and write transactions through the JTAG primary component to interact with the connected secondary peripherals.
System Console provides visibility into your design and allows you to perform system-level debug on an FPGA at run-time. System Console performs tests on debug-enabled Intel® FPGA IP. A variety of debug services provide read and write access to elements in your design.
- Perform board bring-up with finalized or partially complete designs.
- Automate run-time verification through scripting across multiple devices.
- Debug transceiver links, memory interfaces, and Ethernet interfaces.
- Integrate your debug IP into the debug platform.
- Perform system verification with MATLAB* and Simulink.
Please refer to the document for details about the design.
Prepare the design template in the Quartus Prime software GUI
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.