Agilex™ 7 FPGA – Safe Drive-On-Chip Design Example

This design demonstrates how to achieve IEC 61508 SIL 2 and ISO 13849 Cat 3 PLd safety certification using Agilex™ 7 SoC devices. The design is based on the TÜV Rheinland approved Intel Cyclone V SoC FPGA Cat 3 PLd and SIL 2 safety concept Altera does not intend you to certify the design. Therefore, Altera only applies the safety design process described in IEC 61508 only where relevant. The design shows how you apply the Altera SoC FPGA Cat 3 PL d and SIL 2 safety concept. The architecture is based around a particular component of the drive-on-chip, the speed limit. You can extend the concept to monitor, cross-compare, and control other relevant physical and logical variables that are key for safety.

This design demonstrates synchronous control of up to two three-phase permanent magnet synchronous motors (PMSMs) or brushless DC (BLDC) motors. The design includes a motor and power board model that removes the need for a physical motor setup.

This design is an extension of the existing Drive-on-Chip Design Example for Agilex™ 7 Devices. It includes safety function to demonstrate how Agilex™ 7 SoC devices may achieve IEC 61508 SIL 2 or ISO 13849 Cat 3 PL d safety certification.

You need an Agilex™ 7 F-series FPGA Development Kit to run the design. The motor and power model helps you tune and test the control system before using a physical power stage. The motor and power board model are based on the former Tandem Motion 48 V board, described in AN 994 Drive-on-Chip Design Example for Agilex™ 7 Devices.