815955
1/12/2024

Introduction

Arria® 10 FPGA - Signal Tap Logic Analyzer Getting Started Design Example

Design Details

Device Family

Intel® Arria® 10 SX 660 FPGA 10AS066N3F40E2SG

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

23.4

IP Cores (0)

Detailed Description

A simple counter-up design that consists of 2 counters. Counter 1 counts from the range of 0 - 49,999,999 and reset. For every 49,999,999 reached by Counter 1, Counter 2 increments the counter by 1 in the range of 0 - 9 and is stored as an output. Another output corresponds to the value of Counter 2 by storing the value (seven_seg) and representing the value in common anode seven segments binary representation. 


Signal Tap debugging tool using pre-existing setup. By following the user guide, an exercise is provided for the user to learn different signal configuration setups in Signal Tap by changing pre-existing Signal Tap configuration.


Please refer to the document for details about the design.

Prepare the design template in the Quartus Prime software GUI

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.

Design Details

Device Family

Intel® Arria® 10 SX 660 FPGA 10AS066N3F40E2SG

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

23.4