Stratix® 10 FPGA – Hello World on the Nios® V/m Processor Design Example

Stratix® 10 FPGA – Hello World on the Nios® V/m Processor Design Example

787044
8/25/2023
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Introduction

Nios® V/m-based Helloworld example design on the Intel® Stratix® 10 FPGA

Development Kit

Intel® Stratix® 10 SX SoC Development Kits

Design Details

Device Family

Intel® Stratix® 10 SX SoC FPGA

Intel® Stratix® 10 SX 2800 FPGA 1SX280LU2F50E2VG
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

23.2
IP Cores (1)
IP Core IP Core Category
Nios® V/m Processor Intel FPGA IP Embedded Processor

Detailed Description

Please refer to the document for details about the design.

Prepare the design template in the Quartus Prime software GUI

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.

Development Kit

Intel® Stratix® 10 SX SoC Development Kits

Design Details

Device Family

Intel® Stratix® 10 SX SoC FPGA

Intel® Stratix® 10 SX 2800 FPGA 1SX280LU2F50E2VG
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

23.2