Introduction
This design demonstrates the serial loopback via QSFPDD function on the Intel Agilex® 7 FPGA F-Series Development Kit (2x F-Tile).
IP Cores
(4)
| IP Core | IP Core Category |
|---|---|
| F-Tile PMA/FEC Direct PHY Intel FPGA IP | Transceiver PHY |
| Mailbox Client Intel FPGA IP | Configuration and Programming |
| Nios V/m Processor Intel FPGA IP | Embedded Processors |
| F-Tile Reference and System PLL Clocks Intel FPGA IP | Transceiver PHY |
Detailed Description
Uses Intel Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) as platform for demonstration.
Uses 2 Native PHY’s with each 4 independent physical lanes connected to QSFPDD0 and QSFPDD1 and each channel configured in RSFEC53Gpbs PAM4 using 8 FGT’s located in Quad 3 and Quad 1.
