Introduction
This design demonstrates the serial loopback via QSFPDD on Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile)
IP Cores
(4)
| IP Core | IP Core Category |
|---|---|
| F-Tile PMA/FEC Direct PHY Intel FPGA IP | Transceiver PHY |
| Mailbox Client Intel FPGA IP | Configuration and Programming |
| Nios V/m Processor Intel FPGA IP | Embedded Processors |
| F-Tile Reference and System PLL Clocks Intel FPGA IP | Transceiver PHY |
Detailed Description
Please refer to the document for details about the design.
Prepare the design template in the Quartus Prime software GUI
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.