Arria® 10 FPGA – μC/OS-II* RTOS with IPerf for the Nios® V/m Processor Design Example

Arria® 10 FPGA – μC/OS-II* RTOS with IPerf for the Nios® V/m Processor Design Example

763970
12/17/2022
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Introduction

This Nios® V processor-based design incorporates the μC/IPerf, an IPerf 2 server or client developed for the μC/TCP-IP Stack and the μC/OS-II* RTOS.

Development Kit

Intel® Arria® 10 SX SoC Development Kits

Design Details

Device Family

Intel® Arria® 10 SX SoC FPGA
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

22.4
Other Tags

Validated in Quartus and Board
IP Cores (3)
IP Core IP Core Category
Nios V/m Processor Intel FPGA IP EmbeddedProcessor
Triple-Speed Ethernet Intel FPGA IP Ethernet
altera_msgdma DMA

Detailed Description

Perf 2 is a benchmarking tool for measuring performance between two systems, and it can be used as a server or a client. 

An iPerf server receives iPerf request sent over a TCP/IP connection from any iPerf clients, and runs the iPerf test according to the provided arguments.  

Each test reports the bandwidth, loss and other parameters. 

Development Kit

Intel® Arria® 10 SX SoC Development Kits

Design Details

Device Family

Intel® Arria® 10 SX SoC FPGA
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

22.4
Other Tags

Validated in Quartus and Board