Arria 10 - Nios II Simple Socket Server Design Example

714912
5/18/2018

Introduction

This design example shows a socket server using the NicheStack TCP/IP stack-Nios II Edition on MicroC/OS-II on a Arria 10 SoC development board. The server implements simple commands to control board LEDs through a separate MicroC/OS-II task.
IP Cores (31)
IP Core IP Core Category
Top level generated instrumentation fabric Debug & Performance
Altera Arria 10 XCVR Reset Sequencer Other
Avalon-ST Adapter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Nios II Gen2 Processor NiosII
On-Chip Memory (RAM or ROM) OnChipMemory
IRQ Mapper QsysInterconnect
JTAG UART ConfigurationProgramming
PIO (Parallel I/O) Other
MM Interconnect QsysInterconnect
Avalon-ST Error Adapter QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Memory-Mapped Router QsysInterconnect
Reset Controller QsysInterconnect
Interval Timer Peripherals
System ID Peripheral Other
Modular Scatter-Gather DMA BridgesAndAdaptors
Modular SGDMA Dispatcher BridgesAndAdaptors
Modular SGDMA Prefetcher mSGDMA Sub-core
Write Master QsysInterconnect
Read Master QsysInterconnect
Triple-Speed Ethernet Ethernet
Arria 10 Transceiver Native PHY TransceiverPHY
Arria 10 Transceiver ATX PLL TransceiverPLL

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 17.1.0 Pro


Tags Details

  • Intel® FPGAs
  • FPGA Design Store
  • Intel® Arria® 10 SX SoC Development Kits
  • Avalon-ST Adapter Intel® FPGA IP
  • Avalon-ST Timing Adapter Intel® FPGA IP
  • Nios® II Processor
  • On-Chip Memory (RAM or ROM) Intel® FPGA IP
  • IRQ Mapper Intel® FPGA IP
  • JTAG UART Intel® FPGA IP
  • PIO (Parallel I O) Intel® FPGA IP
  • Memory Mapped
  • Avalon-ST Error Adapter Intel® FPGA IP
  • Memory Mapped Demultiplexer
  • Memory-Mapped Multiplexer Intel® FPGA IP
  • Avalon-MM Master Agent Intel® FPGA IP
  • Memory-Mapped Traffic Limiter Intel® FPGA IP
  • Avalon-MM Master Translator Intel® FPGA IP
  • Avalon-MM Slave Agent Intel® FPGA IP
  • Avalon-ST Single Clock FIFO Intel® FPGA IP
  • Avalon-MM Slave Translator Intel® FPGA IP
  • Memory Mapped Router
  • Reset Controller Intel® FPGA IP
  • Interval Timer Intel® FPGA IP
  • System ID Peripheral Intel® FPGA IP
  • Modular Scatter-Gather DMA Intel® FPGA IP
  • Modular SGDMA Dispatcher Intel® FPGA IP
  • Modular SGDMA Prefetcher Intel® FPGA IP
  • Write Master Intel® FPGA IP
  • Read Master Intel® FPGA IP
  • Triple-Speed Ethernet Intel® FPGA IP
  • Transceiver Native PHY Intel® Arria® 10 Cyclone® 10 FPGA IP
  • Transceiver ATX PLL Intel® Arria® 10 Cyclone® 10 FPGA IP
  • Intel® Quartus® Prime Pro Edition
  • 17.1
  • Intel® Arria® 10 FPGAs and SoC FPGAs