Introduction
Development Kit
| IP Core | IP Core Category |
|---|---|
| PIO (Parallel I/O) | Other |
| Nios II Gen2 Processor | NiosII |
| Nios II Gen2 Processor Unit | NiosII |
| IRQ Mapper | QsysInterconnect |
| IRQ Clock Crosser | QsysInterconnect |
| MM Interconnect | QsysInterconnect |
| Avalon-ST Adapter | QsysInterconnect |
| Avalon-ST Error Adapter | QsysInterconnect |
| Memory-Mapped Demultiplexer | QsysInterconnect |
| Memory-Mapped Multiplexer | QsysInterconnect |
| Avalon-ST Handshake Clock Crosser | QsysInterconnect |
| Avalon-MM Slave Agent | QsysInterconnect |
| Avalon-ST Single Clock FIFO | QsysInterconnect |
| Avalon-MM Slave Translator | QsysInterconnect |
| Avalon-MM Master Agent | QsysInterconnect |
| Avalon-MM Master Translator | QsysInterconnect |
| Memory-Mapped Burst Adapter | QsysInterconnect |
| Memory-Mapped Router | QsysInterconnect |
| Altera Avalon Mutex | QsysInterconnect |
| Altera Serial Flash Controller | Flash |
| Altera ASMI Parallel | ConfigurationProgramming |
| Altera EPCQ Serial Flash controller core | ConfigurationProgramming |
| JTAG UART | ConfigurationProgramming |
| On-Chip Memory (RAM or ROM) | OnChipMemory |
| Reset Controller | QsysInterconnect |
| System ID Peripheral | Other |
| Interval Timer | Peripherals |
| Altera IOPLL | ClocksPLLsResets |
Detailed Description
This short abstract provides some details on a reference design objectives and architecture Using Qsys, we build a multiprocessor system containing four processors. Each processor is in a subsystem, creating a hierarchy with four subsystems with a separate memory map, coordinated with pipeline bridges.
Multiprocessor systems possess the benefit of increased performance, but nearly always at the price of significantly increased system complexity for both hardware and software. The idea of using multiple processors to perform different tasks and functions on different processors in real-time embedded applications is gaining popularity. Intel FPGAs provide an ideal platform for developing embedded multiprocessor systems, since the hardware can easily be modified and tuned using Qsys tool to provide optimal system performance. Increases in the size of FPGAs make possible system designs with many Nios II processors on a single chip. Furthermore, with a powerful integration tool like Qsys, different system configurations can be designed, built, and evaluated very quickly. Qsys enables hierarchical designs, reducing system complexity through compartmentalization of the design into discrete subsystems. Each subsystem exports user-defined interfaces, linking the subsystem hierarchy together.
Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
Prepare the design template in the Quartus Prime software command-line
At the command-line, type the following command:
quartus_sh --platform_install -package <project directory>/<project>.par
Once the process completes, then type:
quartus_sh --platform -name <project>
Note:
* ACDS Version: 17.0.0 Standard