Introduction
Development Kit
IP Core | IP Core Category |
---|---|
JTAG Debug Link (internal module) | ConfigurationProgramming |
Avalon-ST Bytes to Packets Converter | QsysInterconnect |
Avalon-ST Single Clock FIFO | QsysInterconnect |
Avalon-ST Timing Adapter | QsysInterconnect |
Avalon-ST JTAG Interface | QsysInterconnect |
Avalon-ST Packets to Bytes Converter | QsysInterconnect |
Avalon MM Debug Fabric | QsysInterconnect |
MM Interconnect | QsysInterconnect |
Avalon-ST Pipeline Stage | QsysInterconnect |
Avalon-ST Adapter | QsysInterconnect |
Avalon-ST Error Adapter | QsysInterconnect |
Avalon-MM Slave Agent | QsysInterconnect |
Avalon-MM Slave Translator | QsysInterconnect |
Memory-Mapped Demultiplexer | QsysInterconnect |
Memory-Mapped Multiplexer | QsysInterconnect |
Memory-Mapped Router | QsysInterconnect |
Avalon-MM Master Agent | QsysInterconnect |
Memory-Mapped Traffic Limiter | QsysInterconnect |
Avalon-MM Master Translator | QsysInterconnect |
Trace ROM | QsysInterconnect |
Avalon Packets to Transaction Converter | QsysInterconnect |
Avalon ST Debug Fabric | QsysInterconnect |
Avalon-ST Demultiplexer | QsysInterconnect |
Avalon-ST Dual Clock FIFO | QsysInterconnect |
Avalon-ST Channel Adapter | QsysInterconnect |
Altera Management Reset Block | Other |
Reset Controller | QsysInterconnect |
Avalon-ST Multiplexer | QsysInterconnect |
Arria 10 Hard IP for PCI Express | PCIExpress |
Arria 10 FPLL | ClocksPLLsResets |
Arria 10 Transceiver ATX PLL | TransceiverPLL |
Arria 10 Transceiver Native PHY | TransceiverPHY |
Arria 10 External Memory Interfaces | ExternalMemoryInterfaces |
EMIF Core Component for 20nm Families | ExternalMemoryInterfaces |
Avalon-MM Pipeline Bridge | QsysInterconnect |
On-Chip Memory (RAM or ROM) | OnChipMemory |
Arria 10 External Memory Interfaces Debug Component | ExternalMemoryInterfaces |
alt_mem_if JTAG to Avalon Master Bridge | BridgesAndAdaptors |
Avalon-MM Clock Crossing Bridge | QsysInterconnect |
Memory-Mapped Width Adapter | QsysInterconnect |
Memory-Mapped Burst Adapter | QsysInterconnect |
Detailed Description
1 (for RTL re-generation)
A PC provides a PCI Express Gen3 x8 slot
All reference designs have been tested with Intel Sandy Bridge
The attached reference design (The SOF is available in the folder pcie_quartus_files as top.sof)
Arria 10 GX FPGA Development Kit (Refer the link for Arria 10 FPGA development Kit : https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html)
A system with either 32-bit / 64-bit Linux or 64-bit Windows installed
Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
Prepare the design template in the Quartus Prime software command-line
At the command-line, type the following command:
quartus_sh --platform_install -package <project directory>/<project>.par
Once the process completes, then type:
quartus_sh --platform -name <project>
Note:
* ACDS Version: 16.1.0 Standard