Agilex™ 3 Ethernet Intel® FPGA Hard IP Register Map

Description

The GTS Ethernet Intel® FPGA Hard IP contains a hardened Ethernet stack and synthesizable soft logic. It can support a 10G data rate with an optional Firecode FEC. The Agilex™ 3 Register Map provides a comprehensive set of registers for configuring and accessing both the Hard IP blocks and soft logic blocks.