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Description
The Fronthaul Compression Intel® FPGA IP consists of compression and decompression for U-plane IQ data. The compression engine computes µ-law or block floating-point compression based on user data compression header (udCompHdr). This IP uses an Avalon streaming interface for IQ data, conduit signals, and for metadata and sideband signals, and Avalon memory-mapped interface for control and status registers (CSRs).