Cyclone® IV Device Handbook, Volume 2, Chapter 1: Transceivers Architecture

Describes the cyclical redundancy check (CRC) error detection feature in user mode and how to recover from soft errors.

This chapter provides features and details on how LEs work, how LABs contain groups of LEs, and how LABs interface with the other blocks in Cyclone® IV devices.

Describes and provides examples about the different modes to dynamically reconfigure different portions of the transceivers without powering down any part of the device.

Describes the memory interface pin support and the external memory interface. Cyclone® IV devices can easily interface with a broad range of external memory devices, including DDR2 SDRAM, DDR SDRAM, and QDR II SRAM.

Describes the hierarchical clock networks and phase locked loops (PLLs). Reconfigure the PLL counter clock frequency and phase shift in real time and dynamically adjust the output clock phase shift.

Describes the configuration and remote system upgrades using volatile SRAM cells to store configuration data.

Cyclone® IV Device Handbook, Volume 3: Device Datasheet

Cyclone® IV Device Handbook, Volume 2: Transceivers

Describes information about external power supply requirements, hot socketing specifications, power-on reset (POR) requirements, and their implementation in Cyclone® IV devices.

Describes the boundary-scan test (BST) features that support IEEE Std. 1149.1 and IEEE Std. 1149.6. The IEEE Std. 1149.6 (AC JTAG) is only supported on the high-speed serial interface (HSSI) transceivers in Cyclone® IV GX devices.

Built on an optimized low-power process, the Cyclone® IV device family offers lowest power, high functionality with the lowest cost with 3.125 Gbps transceivers

Describes the electrical and switching characteristics including operating conditions, power consumption, transceiver specifications, transceiver core, and periphery performance.

Embedded memory structure consists of columns of M9K memory blocks configured to provide various memory functions, such as RAM, shift registers, ROM, and FIFO buffers.

A combination of on chip resources and external interfaces that help increase performance, reduce system cost, and lower the power consumption of digital signal processing (DSP) systems.

Describes the I/O and high speed I/O capabilities driven by the diversification of I/O standards in many low cost applications, and the significant increase in required I/O performance.

Cyclone® IV Device Handbook, Volume 1: Device Core, I/O Interfaces, and System Integration

Multiple reset signals control the transceiver channels independently. Individual reset signals for each channel instantiated and one power-down signal for each transceiver block.