Implementing the Hybrid Memory Cube Controller IP in an Altera FPGA

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Intel® FPGA Training Catalog Altera® FPGA IP Resource and Documentation Collection Altera® FPGA IP Resource and Documentation Collection

653000
2021-09-08
Public

Description

Hybrid Memory Cube, or HMC, is the next generation of high-speed external memory technology. Multiple DRAM layers are connected to a logic base layer to form a 3-D, high capacity, small footprint package. Instead of the parallel interface used in traditional DDR-type memory, HMC uses high-speed transceiver links, abstracting away the complexities of DRAM timing. In this training, you'll learn how to add the HMC Controller IP to your Arria 10 design. You'll know how to generate an example design that can help you get started quickly. You'll learn about the additional blocks that need to be added to complete the design, including an I2C master and one or more transmit PLLs. In the process, you'll learn about transceiver clocking options in Arria 10 devices.

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