Signal Tap Logic Analyzer: Data Acquisition & Additional Features

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Intel® FPGA Development Tools Support Intel® FPGA Training Catalog

652945
2021-12-17
Public

Description

This training is part 4 of 4. The SignalTap® II embedded logic analyzer (ELA) is a system-level debugging tool that monitors the state of internal FPGA design signals and triggers on custom, user-defined conditions during run-time operation of the device without having to bring signals out to device I/O pins. It integrates directly into your design, making it easy to perform functional debug. This final part of the training discusses how to run the logic analyzer to capture monitored signal data and how to analyze the captured data in a number of different formats. You'll also learn about many additional features of the tool, such as the creation and use of power-up triggers, advanced triggers, and how to debug a design using the ELA from a remote location.

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This training is part 1 of 4. The Signal Tap embedded logic analyzer (ELA) is a system-level debugging tool that monitors the state of internal FPGA design signals and triggers on custom, user-defined conditions during run-time operation of the device without having to bring signals out to device I/O pins. It integrates directly into your design, making it easy to perform functional debug. This part of the training introduces you to the ELA and its many features. You'll also learn about the Signal Tap debugging process flow and how to get started using the tool. Use this training as a Quick Start guide for debugging your designs.
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This training is part 3 of 4. The Signal Tap embedded logic analyzer (ELA) is a system-level debugging tool that monitors the state of internal FPGA design signals and triggers on custom, user-defined conditions during run-time operation of the device without having to bring signals out to device I/O pins. It integrates directly into your design, making it easy to perform functional debug. This part of the training discusses the state-based triggering flow and the process of compiling a project that includes a logic analyzer instance. This includes a discussion of features and options for minimizing or completely avoiding recompilation time when changes are made to the logic analyzer. The training also shows you how to program a device in preparation for data acquisition and analysis.
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This training is part 2 of 4. The Signal Tap embedded logic analyzer (ELA) is a system-level debugging tool that monitors the state of internal FPGA design signals and triggers on custom, user-defined conditions during run-time operation of the device without having to bring signals out to device I/O pins. It integrates directly into your design, making it easy to perform functional debug. This part of the training goes into detail on how to create basic trigger conditions. It then walks through many of the options found in the Signal Configuration section of the tool, including the selection of a sampling clock, choosing buffer options, and the many ways of performing sample storage qualification.
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