Industry's First FPGA with IEEE 754 Floating Point
High-performance digital signal processing (DSP) applications increasingly need higher precision in a range greater than 18 bits. Many applications are driving this need for higher precision and range, including:
- Radar systems that need to support higher resolution and multi-antenna architectures
- Wireless base station channel cards for multiple-input multiple-output (MIMO) processing
- Medical and test applications for very high-precision filtering and fast Fourier transforms (FFTs)
To meet demands for higher precision signal processing, we have developed the industry's first variable-precision DSP block available in all 28 nm devices.
For 20 nm and 14 nm devices, we revolutionized the DSP blocks to provide the industry’s first DSP block with hardened floating-point multipliers and adders. This latest architectural innovation allows each DSP block to be configured at compile time in an IEEE 754 floating-point, standard-precision (18 bit), or high-precision (27 bit) mode. The variable-precision DSP block is optimized by family to meet the stringent DSP requirements that each Intel® FPGA family is targeting.
For more information, download the The Industry's First Floating-Point FPGA (PDF) backgrounder.
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