仅对英特尔可见 — GUID: mcn1399898319525
Ixiasoft
1.2.2.1.7.1. 单电源供电器件LVDS接收器时序规范
符号 | 参数 | 模式 | –C7, –I7 | –A7 | –C8 | 单位 | |||
---|---|---|---|---|---|---|---|---|---|
最小 | 最大 | 最小 | 最大 | 最小 | 最大 | ||||
fHSCLK | 输入时钟频率(高速I/O性能管脚) | x10 | 5 | 145 | 5 | 97.5 | 5 | 100 | MHz |
x8 | 5 | 145 | 5 | 97.5 | 5 | 100 | MHz | ||
x7 | 5 | 145 | 5 | 97.5 | 5 | 100 | MHz | ||
x4 | 5 | 145 | 5 | 97.5 | 5 | 100 | MHz | ||
x2 | 5 | 145 | 5 | 97.5 | 5 | 100 | MHz | ||
x1 | 5 | 290 | 5 | 195 | 5 | 200 | MHz | ||
HSIODR | 数据速率(高速I/O性能管脚) | x10 | 100 | 290 | 100 | 195 | 100 | 200 | Mbps |
x8 | 80 | 290 | 80 | 195 | 80 | 200 | Mbps | ||
x7 | 70 | 290 | 70 | 195 | 70 | 200 | Mbps | ||
x4 | 40 | 290 | 40 | 195 | 40 | 200 | Mbps | ||
x2 | 20 | 290 | 20 | 195 | 20 | 200 | Mbps | ||
x1 | 10 | 290 | 10 | 195 | 10 | 200 | Mbps | ||
fHSCLK | 输入时钟频率(低速I/O性能管脚) | x10 | 5 | 100 | 5 | 100 | 5 | 100 | MHz |
x8 | 5 | 100 | 5 | 100 | 5 | 100 | MHz | ||
x7 | 5 | 100 | 5 | 100 | 5 | 100 | MHz | ||
x4 | 5 | 100 | 5 | 100 | 5 | 100 | MHz | ||
x2 | 5 | 100 | 5 | 100 | 5 | 100 | MHz | ||
x1 | 5 | 200 | 5 | 200 | 5 | 200 | MHz | ||
HSIODR | 数据速率(低速I/O性能管脚) | x10 | 100 | 200 | 100 | 200 | 100 | 200 | Mbps |
x8 | 80 | 200 | 80 | 200 | 80 | 200 | Mbps | ||
x7 | 70 | 200 | 70 | 200 | 70 | 200 | Mbps | ||
x4 | 40 | 200 | 40 | 200 | 40 | 200 | Mbps | ||
x2 | 20 | 200 | 20 | 200 | 20 | 200 | Mbps | ||
x1 | 10 | 200 | 10 | 200 | 10 | 200 | Mbps | ||
SW | 采样窗口 | — | — | 700 | — | 700 | — | 700 | ps |
tx Jitter | 输入抖动 | — | — | 1,000 | — | 1,000 | — | 1,000 | ps |
tLOCK | PLL从器件配置结束进行锁定所需要的时间。 | — | — | 1 | — | 1 | — | 1 | ms |