仅对英特尔可见 — GUID: edx1554764102817
Ixiasoft
收发器参考时钟规范
符号/说明 | 条件 | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Supported I/O Standards | — | HCSL | — | ||
Input Reference Clock Frequency 123 | — | 99.97 | 100 | 100.03 | MHz |
Rising Edge Rate 124 | PCIe* | 0.6 | — | 4 | V/ns |
Falling Edge Rate124 | PCIe* | 0.6 | — | 4 | V/ns |
Duty cycle | PCIe* | 40 | — | 60 | % |
Spread-spectrum modulating clock frequency | — | 30 | — | 33 | kHz |
Spread-spectrum downspread | — | — | 0 to -0.5 | — | % |
Absolute VMAX | — | — | 1.15 | — | V |
Absolute VMIN | — | — | -0.3 | — | V |
Peak-to-peak differential input voltage | — | 300 | — | 1500 | mV |
VICM (DC coupled) | HCSL I/O standard for PCIe* reference clock | 250 | — | 550 | mV |
Cycle to cycle jitter (TCCJITTER) 125 — | PCIe* | — | — | 150 | ps |
TSSC-MAX-PERIOD-SLEW | Max SSC df/dt | — | — | 1250 | ppm/us |
123 在扩频时钟(SSC)关闭时的数量。
124 在差分波形上从-150 mV到+150 mV测量的。300 mV测量窗口以差分零交叉为中心。
125 对于通用参考时钟架构,请遵循 PCI Express* Card Electromechanical Specification for 2.5 GT/s, Section 4.3.7 Refclk Specifications for 5.0 GT/s and Section 4.3.8 Refclk Specifications for 8.0 GT/s in the PCI Express* Base Specification Revision 3.0, and the Section 8.6 Refclk Specifications for 16.0 GT/s in the PCI Express* Base Specification Revision 4.0中指定的抖动限制。