Nios® V Embedded Processor Design Handbook

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ID 726952
Date 5/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Nios® V Embedded Processor 2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer 3. Nios® V Processor Software System Design 4. Nios® V Processor Configuration and Booting Solutions 5. Nios® V Processor - Using the MicroC/TCP-IP Stack 6. Nios® V Processor Debugging, Verifying, and Simulating 7. Nios® V Processor — Remote System Update 8. Nios® V Processor — Using Custom Instruction 9. Nios® V Embedded Processor Design Handbook Archives 10. Document Revision History for the Nios® V Embedded Processor Design Handbook
1. About the Nios® V Embedded Processor x
1.1. Intel® FPGA and Embedded Processors Overview 1.2. Quartus® Prime Software Support 1.3. Nios® V Processor Licensing 1.4. Embedded System Design
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer x
2.1. Creating Nios® V Processor System Design with Platform Designer 2.2. Integrating Platform Designer System into the Quartus® Prime Project 2.3. Designing a Nios® V Processor Memory System 2.4. Clocks and Resets Best Practices 2.5. Assigning a Default Agent 2.6. Assigning a UART Agent for Printing 2.7. JTAG Signals
2.1. Creating Nios® V Processor System Design with Platform Designer x
2.1.1. Instantiating Nios® V Processor Intel® FPGA IP 2.1.2. Defining System Component Design 2.1.3. Specifying Base Addresses and Interrupt Request Priorities
2.1.1. Instantiating Nios® V Processor Intel® FPGA IP x
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Intel® FPGA IP 2.1.1.2. Instantiating Nios® V/m Microcontroller Intel® FPGA IP 2.1.1.3. Instantiating Nios® V/g General Purpose Processor Intel® FPGA IP
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Intel® FPGA IP x
2.1.1.1.1. Use Reset Request Tab 2.1.1.1.2. Vectors Tab 2.1.1.1.3. ECC Tab
2.1.1.2. Instantiating Nios® V/m Microcontroller Intel® FPGA IP x
2.1.1.2.1. Debug Tab 2.1.1.2.2. Use Reset Request Tab 2.1.1.2.3. Vectors Tab 2.1.1.2.4. CPU Architecture 2.1.1.2.5. ECC Tab
2.1.1.3. Instantiating Nios® V/g General Purpose Processor Intel® FPGA IP x
2.1.1.3.1. Debug Tab 2.1.1.3.2. Use Reset Request Tab 2.1.1.3.3. Vectors Tab 2.1.1.3.4. Memory Configurations Tab 2.1.1.3.5. Custom Instruction Tab 2.1.1.3.6. CPU Architecture 2.1.1.3.7. ECC Tab
2.2. Integrating Platform Designer System into the Quartus® Prime Project x
2.2.1. Instantiating the Nios® V Processor System Module in the Quartus® Prime Project 2.2.2. Connecting Signals and Assigning Physical Pin Locations 2.2.3. Constraining the Intel FPGA Design
2.3. Designing a Nios® V Processor Memory System x
2.3.1. Volatile Memory 2.3.2. Non-Volatile Memory 2.3.3. On-Chip Memory Configuration – RAM or ROM 2.3.4. Caches 2.3.5. Tightly Coupled Memory
2.4. Clocks and Resets Best Practices x
2.4.1. System Clock 2.4.2. Reset Request Interface 2.4.3. Reset Release IP
2.4.2. Reset Request Interface x
2.4.2.1. Typical Use Cases
2.6. Assigning a UART Agent for Printing x
2.6.1. Preventing Stalls by the JTAG UART
3. Nios® V Processor Software System Design x
3.1. Nios V Processor Software Development Flow 3.2. Intel FPGA Embedded Development Tools
3.1. Nios V Processor Software Development Flow x
3.1.1. Board Support Package Project 3.1.2. Application Project
3.2. Intel FPGA Embedded Development Tools x
3.2.1. Nios® V Processor Board Support Package Editor 3.2.2. RiscFree* IDE for Intel FPGAs 3.2.3. Eclipse CDT for Embedded C/C++ Developer 3.2.4. Nios V Utilities Tools 3.2.5. File Format Conversion Tools 3.2.6. Other Utilities Tools
4. Nios® V Processor Configuration and Booting Solutions x
4.1. Introduction 4.2. Linking Applications 4.3. Nios® V Processor Booting Methods 4.4. Introduction to Nios® V Processor Booting Methods 4.5. Nios® V Processor Booting from Configuration QSPI Flash 4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM) 4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM) 4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
4.2. Linking Applications x
4.2.1. Linking Behavior
4.2.1. Linking Behavior x
4.2.1.1. Default BSP Linking 4.2.1.2. Configurable BSP Linking
4.4. Introduction to Nios® V Processor Booting Methods x
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash 4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier 4.4.3. Nios® V Processor Application Execute-In-Place from OCRAM 4.4.4. Nios® V Processor Application Execute-In-Place from TCM
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash x
4.4.1.1. alt_load()
4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier x
4.4.2.1. GSFI Bootloader 4.4.2.2. SDM Bootloader
4.5. Nios® V Processor Booting from Configuration QSPI Flash x
4.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) 4.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
4.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) x
4.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash 4.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) 4.5.1.3. GSFI Bootloader Example Design
4.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash x
4.5.1.1.1. Hardware Design Flow 4.5.1.1.2. Software Design Flow 4.5.1.1.3. Programming Files Generation 4.5.1.1.4. QSPI Flash Programming
4.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) x
4.5.1.2.1. Hardware Design Flow 4.5.1.2.2. Software Design Flow 4.5.1.2.3. Programming Files Generation 4.5.1.2.4. QSPI Flash Programming
4.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices) x
4.5.2.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader) 4.5.2.2. SDM Bootloader Example Design
4.5.2.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader) x
4.5.2.1.1. Hardware Design Flow 4.5.2.1.2. Software Design Flow 4.5.2.1.3. Software Design Flow (SDM Bootloader Project) 4.5.2.1.4. Software Design Flow (User Application Project) 4.5.2.1.5. Programming Files Generation 4.5.2.1.6. QSPI Flash Programming SDM
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM) x
4.6.1. Nios® V Processor Application Executes in-place from OCRAM
4.6.1. Nios® V Processor Application Executes in-place from OCRAM x
4.6.1.1. Hardware Design Flow 4.6.1.2. Software Design Flow 4.6.1.3. Programming
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM) x
4.7.1. Nios® V Processor Application Executes in-place from TCM
4.7.1. Nios® V Processor Application Executes in-place from TCM x
4.7.1.1. Hardware Design Flow 4.7.1.2. Software Design Flow 4.7.1.3. Programming
5. Nios® V Processor - Using the MicroC/TCP-IP Stack x
5.1. Introduction 5.2. Software Architecture 5.3. Support and Licensing 5.4. MicroC/TCP-IP Example Designs 5.5. Development Flow 5.6. Operating the Example Designs 5.7. Optional Configuration 5.8. MicroC/TCP-IP Simple Socket Server Concepts
5.4. MicroC/TCP-IP Example Designs x
5.4.1. Hardware and Software Requirements 5.4.2. Overview 5.4.3. Acquiring the Example Design Files 5.4.4. Hardware Design Files 5.4.5. Software Design Files
5.4.5. Software Design Files x
5.4.5.1. MicroC/TCP-IP IPerf Example Design 5.4.5.2. MicroC/TCP-IP Simple Socket Server Example Design
5.5. Development Flow x
5.5.1. Hardware Development Flow 5.5.2. Software Development Flow 5.5.3. Device Programming
5.5.2. Software Development Flow x
5.5.2.1. Creating a BSP project 5.5.2.2. Configuring the BSP 5.5.2.3. Creating an Application Project 5.5.2.4. Building the Application Project
5.6. Operating the Example Designs x
5.6.1. Operating the MicroC/TCP-IP IPerf 5.6.2. Operating the MicroC/TCP-IP Simple Socket Server
5.7. Optional Configuration x
5.7.1. Configuring Hardware Name 5.7.2. Configuring MAC and IP Addresses 5.7.3. Configuring MicroC/TCP-IP Initialization 5.7.4. Configuring iPerf Server Auto-Initialization
5.7.3. Configuring MicroC/TCP-IP Initialization x
5.7.3.1. Network Task Configuration 5.7.3.2. Network Interface Configuration
5.8. MicroC/TCP-IP Simple Socket Server Concepts x
5.8.1. MicroC/OS-II Resources 5.8.2. Error Handling 5.8.3. MicroC/TCP-IP Stack Default Configuration
6. Nios® V Processor Debugging, Verifying, and Simulating x
6.1. Debugging Nios® V/c Processor 6.2. Debugging Nios® V Processor Hardware Designs 6.3. Debugging Nios® V Processor Software Designs 6.4. Debugging Tools 6.5. Additional Embedded Design Considerations 6.6. Simulating Nios® V Processor Designs
6.1. Debugging Nios® V/c Processor x
6.1.1. Pilot System with Non-pipelined Nios V/m Processor 6.1.2. printf() Debugging
6.2. Debugging Nios® V Processor Hardware Designs x
6.2.1. JTAG Server System Response to JTAG Server 6.2.2. System Console 6.2.3. Signal Tap Logic Analyzer 6.2.4. In-System Sources and Probes
6.2.2. System Console x
6.2.2.1. JTAG to Avalon® Host Bridge Core
6.3. Debugging Nios® V Processor Software Designs x
6.3.1. Ashling* RiscFree* IDE for Intel® FPGAs 6.3.2. OpenOCD 6.3.3. Objdump File 6.3.4. Show Make Commands
6.5. Additional Embedded Design Considerations x
6.5.1. JTAG Signal Integrity 6.5.2. Additional Memory Space for System Prototyping
6.6. Simulating Nios® V Processor Designs x
6.6.1. Prerequisites 6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer 6.6.3. Creating Nios V Processor Software 6.6.4. Generating Memory Initialization File 6.6.5. Generating System Simulation Files 6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer x
6.6.2.1. Using IP and Platform Designer Simulation Setup Scripts
6.6.3. Creating Nios V Processor Software x
6.6.3.1. Generating the Board Support Package 6.6.3.2. Generating the Application Project File 6.6.3.3. Building the Application Project
7. Nios® V Processor — Remote System Update x
7.1. Overview 7.2. Quartus® Prime Pro Edition Software and Tool Support 7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices
7.2. Quartus® Prime Pro Edition Software and Tool Support x
7.2.1. Intel® Quartus® Prime Pro Edition Software 7.2.2. Programming File Generator
7.2.1. Intel® Quartus® Prime Pro Edition Software x
7.2.1.1. Setting Max Retry Parameter 7.2.1.2. Selecting Factory Load Pin
7.2.2. Programming File Generator x
7.2.2.1. Programming File Generator File Types 7.2.2.2. Bitswap Option 7.2.2.3. Quartus® Prime Programmer 7.2.2.4. Supported QSPI Flash Devices
7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices x
7.3.1. Individual Factory, Application, and Update Images 7.3.2. Hardware Design Flow 7.3.3. Software Design Flow 7.3.4. Individual Images Generation 7.3.5. Remote System Update Image Files Generation 7.3.6. QSPI Flash Programming 7.3.7. Operating the RSU Client API
7.3.2. Hardware Design Flow x
7.3.2.1. Create a Platform Designer System 7.3.2.2. Quartus® Prime Software Settings
7.3.3. Software Design Flow x
7.3.3.1. Generating the ZLIB libraries 7.3.3.2. Creating a Board Support Package Project 7.3.3.3. Configuring and Generating the BSP Project 7.3.3.4. Creating Multiple Application Projects 7.3.3.5. Building the Application Projects 7.3.3.6. Generating HEX Files
7.3.5. Remote System Update Image Files Generation x
7.3.5.1. Generating Initial RSU Image Using SOF file 7.3.5.2. Generating an Application Update Image 7.3.5.3. Generating a Factory Update Flash Image
7.3.6. QSPI Flash Programming x
7.3.6.1. Programming the Initial RSU Image 7.3.6.2. Programming the Update Images
7.3.7. Operating the RSU Client API x
7.3.7.1. Trigger Reconfiguration Menu with Selected Image 7.3.7.2. Updating an Application Image 7.3.7.3. Updating the Factory Image
8. Nios® V Processor — Using Custom Instruction x
8.1. Introduction 8.2. Unimplemented Instruction Example Design 8.3. Hardware Acceleration Example Design
8.2. Unimplemented Instruction Example Design x
8.2.1. Hardware and Software Requirements 8.2.2. Overview 8.2.3. Acquiring the Example Design File 8.2.4. Hardware Design Files 8.2.5. Software Design Files 8.2.6. Development Flow 8.2.7. Operating the Example Design
8.2.6. Development Flow x
8.2.6.1. Hardware Development Flow 8.2.6.2. Software Development Flow 8.2.6.3. Device Programming
8.3. Hardware Acceleration Example Design x
8.3.1. Hardware and Software Requirements 8.3.2. Overview 8.3.3. Acquiring the Example Design File 8.3.4. Hardware Design Files 8.3.5. Software Design Files 8.3.6. Development Flow 8.3.7. Operating the Example Design
8.3.6. Development Flow x
8.3.6.1. Hardware Development Flow 8.3.6.2. Software Development Flow 8.3.6.3. Device Programming
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook

6.2.1. JTAG Server

A JTAG Server communicates with the hardware and allows multiple programs to use JTAG resources concurrently. You can display the connected devices' JTAG scan chain to validate the Nios® V processor's presence in the Intel FPGA.

From the Nios® V Command Shell, the jtagconfig -d command identifies available JTAG devices and the number of CPUs in the subsystem connected to each JTAG device. The example below shows the system response to a jtagconfig -d command.

System Response to JTAG Server

$ jtagconfig -d
1) AGF FPGA Development Kit on Intel® FPGA Download Cable [USB-0]
   (JTAG Server Version 22.1.0 Build 174 03/30/2022 SC Pro Edition)
  C341A0DD   AGFB014R24A(.|R1|R2)/.. (IR=10)
    Design hash    74DFB795DF11A555CEDF
    + Node 00486E00  Source/Probe #0
    + Node 08986E00  Nios V #0
    + Node 0C006E00  JTAG UART #0
  031830DD   10M16S(A|C|L) (IR=10)

  Captured DR after reset = (30D068376063061BB020D10DD) [98]
  Captured IR after reset = (006AAD55) [32]
  Captured Bypass after reset = (0A) [5]
  Captured Bypass chain = (00) [5]
  JTAG clock speed auto-adjustment is enabled. To disable, set JtagClockAutoAdjust parameter to 0
  JTAG clock speed 24 MHz

The response in the example lists one FPGA connected to the running JTAG server through Intel FPGA Download Cable. The cable attached to the USB-0 port is connected to a JTAG node in a Platform Designer subsystem with a single Nios® V processor core.

The node numbers represent JTAG nodes inside the FPGA.
  • The appearance of node number 0x08986Exx confirms that the FPGA implementation has a Nios® V processor with a JTAG debug module. The CPU instances are identified by the least significant byte of the nodes after 0x08986E.
  • The appearance of node number 0x0C006Exx confirms that the FPGA implementation has a JTAG UART component. The JTAG UART instances are identified by the least significant byte of the nodes after 0x0C006E.

All instance IDs begin with 0. Only the CPUs that have debug enabled appear in the listing. Use this listing to confirm that you have debug enabled for the Nios® V processors you intended.

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