Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

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ID 683788
Date 10/08/2019
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide 2. Developing an Intel Arria 10 SoC Custom Platform 3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform 4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide Archives 5. Document Revision History for Intel® FPGA SDK for OpenCL™ : Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide x
1.1. Intel Arria 10 SoC Development Kit Reference Platform: Prerequisites 1.2. Features of the Intel Arria 10 SoC Development Kit Reference Platform 1.3. Intel Arria 10 SoC Development Kit Reference Platform Board Variants 1.4. Contents of the Intel Arria 10 SoC Development Kit Reference Platform 1.5. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.0 to 17.1 1.6. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.1.2 to 18.0
2. Developing an Intel Arria 10 SoC Custom Platform x
2.1. Initializing an Intel Arria 10 SoC Custom Platform 2.2. Modifying Your Intel Arria 10 SoC Custom Platform 2.3. Integrating Your Intel Arria 10 SoC Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Changing the Device Part Number 2.5. Modifying the Kernel PLL Reference Clock 2.6. Modifying the Hard Processor System 2.7. Guaranteeing Timing Closure in the Intel Arria 10 SoC Custom Platform 2.8. Generating the base.qar Post-Fit Netlist for Your Intel Arria 10 SoC FPGA Custom Platform
3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform x
3.1. Compiling the Device Tree Blob 3.2. Compiling the Linux Kernel for the Intel Arria 10 SoC Development Kit 3.3. Compiling the OpenCL Linux Kernel Driver 3.4. Generating Full-Chip Programming File for SD Card Image 3.5. Building the SD Card Image 3.6. Known Issues
3.5. Building the SD Card Image x
3.5.1. Layout of the OpenCL Micro SD Card 3.5.2. Creating the SD Card Image 3.5.3. Guidelines on Imaging the Micro SD Card
3.5.2. Creating the SD Card Image x
3.5.2.1. Creating Partition 1 of the SD Card Image 3.5.2.2. Creating Partition 2 of the SD Card Image 3.5.2.3. Creating Partition 3 of the SD Card Image
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide
2. Developing an Intel Arria 10 SoC Custom Platform
3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform
4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide Archives
5. Document Revision History for Intel® FPGA SDK for OpenCL™ : Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

1.6. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.1.2 to 18.0

Following is a list of what has changed in a10soc Reference Platform from 17.1.2 to 18.0 release:
High-level changes include:
  • Various clean up of import_compile.tcl, pre_flow_pr, post_flow_pr
  • Clean up of old top_synth revision (migrated to new simplified PR flow)
  • Fix for write .sdc, in base_write_sdc.tcl
  • AOC no longer emits .qsys files, it emits just Verilog HDL (kernel_system.v) and injects a .qip file into project. Changes needed:
    • Instantiate module kernel_system from kernel_system.v (in pr_region.v now)
    • If you use add_pipe in board_spec.xml, instantiate pipeline registers in the BSP but within the PR region (see ip/kernel_mem and pr_region.v)
Table 4.  Changes in a10soc Reference Platform from 17.1.2 to 18.0
File Change
base.qar Updated with 18.0 static region.
board_spec.xml Updated version, static region used resources, removed addpipe parameter, which is no longer needed.
top.qpf Removed top_synth revision.
flat.qsf Removal of obsolete assignments.
base.qsf Removed Platform Designer flow.
kernel_system_inst pr_region_inst
top.qsf Simplified PR flow.
opencl_bsp_ip.qsf Removed Platform Designer flow.
top.sdc Removed Platform Designer flow.
import_compile.tcl Removed Platform Designer flow, simplified PR flow.
ip/freeze_wrapper.v Removed Platform Designer flow.
scripts/base_write_sdc.tcl Updated to correct base.sdc ordering.
scripts/post_flow_pr.tcl Updated for fast-compilation
scripts/pre_flow_pr.tcl Updated for fast-compile, removed Platform Designer flow, and cleaned up (moved some functions into OpenCL SDK).
scripts/qar_ip_files.tcl Do not package up opencl_bsp_ip.qsf.
base.qar Updated with 18.0 static region.

Files added:

  • kernel_mem.qsys
  • ip/pr_region.v
  • ip/kernel_mem/kernel_mem_mm_bridge_0.ip
Removed files:
  • top_synth.qsf, which is obsolete because of simplified PR flow.
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