Intel® FPGA SDK for OpenCL™: Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide

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ID 683435
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide x
1.1. Overview of the Cyclone V SoC Development Kit Reference Platform 1.2. Porting the Reference Platform to Your SoC FPGA Board 1.3. Software Support for Shared Memory 1.4. FPGA Reconfiguration 1.5. Building an SD Flash Card Image 1.6. Compiling the Linux Kernel for Cyclone V SoC FPGA 1.7. Known Issues 1.8. Document Revision History
1.1. Overview of the Cyclone V SoC Development Kit Reference Platform x
1.1.1. Cyclone V SoC Development Kit Reference Platform Board Variants 1.1.2. Content of the Cyclone V SoC Development Kit Reference Platform 1.1.3. Relevant Features of the Cyclone V SoC Development Kit
1.1.3. Relevant Features of the Cyclone V SoC Development Kit x
1.1.3.1. Cyclone V SoC Development Kit Reference Platform Design Goals and Decisions
1.2. Porting the Reference Platform to Your SoC FPGA Board x
1.2.1. Updating a Ported Reference Platform
1.4. FPGA Reconfiguration x
1.4.1. FPGA System Architecture Details
1.5. Building an SD Flash Card Image x
1.5.1. Modifying an Existing SD Flash Card Image 1.5.2. Creating an SD Flash Card Image
1.6. Compiling the Linux Kernel for Cyclone V SoC FPGA x
1.6.1. Recompiling the Linux Kernel 1.6.2. Compiling and Installing the OpenCL Linux Kernel Driver
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide

1.1.3.1. Cyclone V SoC Development Kit Reference Platform Design Goals and Decisions

Intel® bases the implementation of the Cyclone™ V SoC Development Kit Reference Platform on several design goals and decisions. Intel® recommends that you consider these goals and decisions when you port this Reference Platform to your SoC FPGA board.

Below are the c5soc design goals:

  1. Provide the highest possible bandwidth between kernels on the FPGA and the DDR memory system(s).
  2. Ensure that computations on the FPGA (that is, OpenCL™ kernels) do not interfere with other CPU tasks that might include servicing peripherals.
  3. Leave as much FPGA resources as possible for kernel computations instead of interface components.

Below are the high-level design decisions that are the direct consequences of Intel® 's design goals:

  1. The Reference Platform only uses hard DDR memory controllers with the widest-possible configuration (256 bits).
  2. The FPGA communicates with the HPS DDR memory controller directly, without involving the AXI bus and the L3 switch inside the HPS. The direct communication provides the best possible bandwidth to DDR, and keeps FPGA computations from interfering with communications between the CPU and its periphery.
  3. Scatter-gather direct memory access (SG-DMA) is not part of the FPGA interface logic. Instead of transferring large amounts of data between DDR memory systems, store the data in the shared HPS DDR. Direct access to CPU memory by the FPGA is more efficient than DMA. It saves hardware resources (that is, FPGA area) and simplifies the Linux kernel driver.
    Warning: Memory transfer between the shared HPS DDR system and the DDR system that is accessible only to the FPGA is very slow. If you choose to transfer memory in this manner, use it for very small amounts of data only.
  4. The host and the device perform non-DMA data transfer between each other via the HPS-to-FPGA (H2F) bridge, using only a single 32-bit port. The reason is, without DMA, the Linux kernel can only issue a single 32-bit read or write request, so it is unnecessary to have a wider connection.
  5. The host sends control signals to the device via a lightweight H2F (LH2F) bridge. Because control signals from the host to the device are low-bandwidth signals, an LH2F bridge is ideal for the task.
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