Boundary-scan test (BST) architecture offers the capability to efficiently test components on PCBs with tight lead spacing. This BST architecture can test pin connections without using physical test probes and capture functional data while a device is operating normally. Boundary-scan cells in a device can force signals onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the boundary-scan cells. Captured data is serially shifted out and externally compared to expected results.
Boundary-scan tools feature an in-system programmability (ISP) capability which utilizes the IEEE Standard 1149.1 controller for Intel® FPGA devices including MAX® II, MAX® 3000A, MAX® 7000AE and MAX® 7000B devices. These devices also support IEEE 1532 programming which utilizes the IEEE Standard 1149.1 Test Access Port (TAP) interface.