The Timing Analyzer is an ASIC-strength static timing analyzer that supports the industry-standard Synopsys® Design Constraints (SDC) format. This page provides links to resources where you can learn more about the Timing Analyzer.
For a brief overview of the Timing Analyzer, refer to the Timing Analyzer section on the Intel® Quartus® Prime Design Software product feature page.
Timing Analyzer Resources
Table 1 provides links to available documentation on the Timing Analyzer.
Table 1. Timing Analyzer Documentation
| Title | Description |
|---|---|
| AN775: I/O Timing Information Generation Guidelines | This Application Note demonstrates techniques to generate I/O timing information for any given device using the Intel® Quartus® Prime software. |
|
(Pro Edition) |
The Intel® Quartus® Prime Pro Edition Timing Analyzer uses industry-standard constraint and analysis methodology to report on all data required times, data arrival times, and clock arrival times for all register-to-register, I/O, and asynchronous reset paths in your design. |
|
(Standard Edition) |
The Intel® Quartus® Prime Standard Edition Timing Analyzer uses industry-standard constraint and analysis methodology to report on all data required times, data arrival times, and clock arrival times for all register-to-register, I/O, and asynchronous reset paths in your design. |
| Applying Multicycle Exceptions in the Timing Analyzer (PDF) | This application note details how to apply multicycle exceptions in the Timing Analyzer. |
| Quartus Prime Timing Analyzer Cookbook (PDF) | This cookbook provides various design examples and templates showing how to apply timing constraints to various design circuits. |
| Timing Analyzer Quick Start Tutorial (PDF) | This tutorial provides a quick introduction to the Timing Analyzer. |
| SDC and Timing Analyzer API Reference Manual (PDF) | This reference manual provides a list of all SDC commands supported by the Timing Analyzer, as well as the complete Tool Command Language (Tcl) API. |
| AN 471: High-Performance FPGA PLL Analysis with Timing Analyzer (PDF) | This application note describes how to analyze and constrain phase-locked loops (PLLs) using the Timing Analyzer. |
| Performing Equivalent Timing Analysis Between Altera Timing Analyzer and Xilinx Trace white paper (PDF) | This white paper shows how to perform equivalent static timing analysis between Altera's Timing Analyzer and Xilinx's Trace. |
| Timing Analyzer Clock Analyzer | Provides detailed information about clock analysis, including derivation of equations for timing analysis. |
| Timing Analyzer Exceptions | Gives an overview of Timing Analyzer SDC exceptions and their precedence. |
| Timing Analyzer Collections | Lists all the supported collections (a core part of the Timing Analyzer). |
| Timing Analyzer GUI | Familiarizes you with the Timing Analyzer GUI and its features. |
Table 2 provides links to available training and demonstrations on the Timing Analyzer.
Table 2. Timing Analyzer Training and Demonstrations
| Title | Description |
|---|---|
|
(Online Course) |
You will learn key aspects of the Timing Analyzer GUI in the Intel® Quartus® Prime Pro software v. 20.3 with emphasis on evaluating timing reports. This is a 1.5-hour online course. |
Constraining Source-Synchronous Interfaces (Online Course) |
This training will show you how to constrain and analyze single data rate source synchronous interfaces with the Timing Analyzer in the Intel® Quartus® Prime software. You will learn the benefits of source synchronous interfaces as compared to common clock system interfaces. You will be able to write Synopsys* Design Constraints (SDC) to constrain single data rate source synchronous inputs and outputs. This is a 1-hour online course. |
Constraining Double Data Rate Source Synchronous Interfaces (Online Course) |
This training provides an introduction to double data rate interfaces and some of the challenges involved in constraining them. You’ll learn about clock constraints, data constraints, and timing exceptions for both input and output DDR interfaces. Finally, you’ll learn how to analyze DDR source synchronous interface timing with the Timing Analyzer timing analyzer. This is a 30-minute online course. |
The Intel® Quartus® Prime Software: Foundation (Instructor-Led Course) |
Learn to use the Intel® Quartus® Prime software to develop an FPGA or CPLD design from initial design to device programming. You'll create a new project, input new or existing design files, and compile your project. You’ll learn how to search for compilation information, use settings and assignments to adjust the results of compilation, and manage I/O-related assignments. This is an 8-hour instructor-led course. |