Automotive Digital Radar Reference Design

Recommended for:

  • Device: Cyclone® V GX

  • Quartus®: v13.0




Intel’s automotive digital radar reference design lets you easily develop and verify hardware accelerators using our advanced development tools. It demonstrates how an FPGA can be used as a hardware accelerator for basic Continuous Wave Frequency Modulation (CWFM) type automotive radars. Its hardware and software design methodology enables you to develop digital radar processing floating-point Fast Fourier Transform (FFT) accelerators, digital beamforming, and fixed-point Finite Impulse Response (FIR) filtering without hand coding Register Transfer Level (RTL). Use this design as a starting point for radar designs to which you can add additional processing algorithms.


The main features of this reference design are:

  • Develop a floating-point FFT hardware accelerator, digital beamformer, and fixed-point FIR filter using our DSP Builder for Intel® FPGAs (advanced blockset) within MATLAB* Simulink. Allows for automatic generation of Register Transfer Level (RTL) from the DSP Builder for Intel FPGAs model.
  • Hardware verification of the DSP Builder model using system in the loop via a MATLAB application program interface (API) developed by Intel. Provides ability to verify the design at system clock speed on actual hardware instead of needing to simulate RTL.
  • Integrates the hardware accelerator into an embedded system using the Platform Designer tool and Nios® processor II as the host.

Demonstrated Intel® Technology:

  • Cyclone V GX FPGA
  • Nios II processor
  • DSP Builder for Intel FPGAs (advanced blockset)
  • Platform Designer
  • Intel® Quartus® Software tool
  • System Console

Figure 1. Automotive digital radar system reference design block diagram.