ModelSim* Tcl Scripting Examples

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Table 1 contains Tcl script examples that demonstrate a setup for Intel® libraries with the Mentor Graphics* ModelSim* SE and PE software. ModelSim*-Altera® edition and ModelSim-Altera Web Edition come with pre-compiled Intel libraries. Table 1 also contains examples that demonstrate a functional simulation for Intel memories and a timing simulation of a phase-locked loop (PLL) circuits inside Intel devices. For more information on Tcl and ModelSim, refer to the Mentor Graphics ModelSim and QuestaSim Support (PDF) chapter of the Quartus® II Handbook (PDF).

Table 1. ModelSim Tcl Script Examples

Tcl Scripts

Description

Library Setup Script (Verilog HDL)

Library Setup Script (VHDL)

These scripts demonstrate how to set up Intel libraries for the ModelSim SE or PE simulator using behavioral simulation library files available in the Quartus II software. These scripts are not intended for use with the ModelSim-Altera software.

Intel Memory Behavioral Simulation

This script demonstrates how to perform a simulation using Intel memory files, including RAM Initialization Files (.rif) and Hexadecimal (Intel-format) Files (.hex)

PLL Post-Fit Timing Simulation

This script demonstrates how to perform a PLL timing simulation using the +transport_int_delays and +transport_path_delays options.