VHDL: Unsigned Multiply-Adder

BUILT IN - ARTICLE INTRO SECOND COMPONENT

This example describes an 8-bit unsigned multiply-adder design with registered I/O ports in VHDL. Synthesis tools detect multiply-adder designs in HDL code and infer altmult_add megafunction.

Figure 1. Unsigned multiply-adder top-level diagram.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Table 1. Unsigned Multiply-Adder Port Listing

Port Name Type Description
a, b, c, d Input 8-bit inputs to multiply-adder unit
clk Input Clock
aclr Input Asynchronous clear
result Output 16-bit output of multiply-adder unit