VHDL: Single-Port ROM

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This example describes a 256-bit x 8-bit single-port ROM design with one address port for read operations in VHDL. Synthesis tools are able to detect ROM designs in the HDL code and automatically infer the altsyncram or lpm_rom megafunctions depending on the target device architecture.

Figure 1. Single-port rom top-level diagram

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Table 1. Single-Port ROM Port Listing

Port Name Type Description
addr[7:0] Input 8-bit read address
clk Input Clock input
q[7:0] Output 8-bit data output