VHDL: Signed Multiplier



This example describes an 8-bit signed multiplier design in VHDL. Synthesis tools detect multiplier designs in HDL code and infer lpm_mult megafunction.

Figure 1. Signed multiplier top-level diagram.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Table 1. Signed Multiplier Port Listing

Port Name Type Description
a[7:0], b[7:0] Input 8-bit data inputs to multiplier unit
result[15:0] Output 16-bit data output of multiplier unit