VHDL: Dual Clock Synchronous RAM



This example describes a 64-bit x 8-bit dual clock synchronous RAM design with separate read and write addresses in VHDL. Synthesis tools are able to detect RAM designs in HDL code and automatically infer the altsyncram or altdpram megafunctions depending on the target device architecture.

Figure 1. Dual clock synchronous RAM top-level diagram.

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