VHDL: 1x64 Shift Register

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This example describes a single-bit wide, 64-bit long shift register in VHDL. Synthesis tools are able to detect groups of shift registers and automatically infer the altshift_taps megafunction. The implementation may be done in device block memory resources depending on the target device architecture.

Figure 1. 1x64 Shift register top-level diagram.

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Table 1 lists the ports in the 1x64 shift register design.

Table 1. 1x64 Shift Register Port Listing

Port Name Type Description
sr_in Input Shift register input
enable Input Shift enable input
clk Input Clock input
sr_out Output Shift register output