This page consists of design examples for state machines in Verilog HDL. A state machine is a sequential circuit that advances through a number of states. The examples provide the HDL codes to implement the following types of state machines:
4-State Mealy State Machine
The outputs of a Mealy state machine depend on both the inputs and the current state. When the inputs change, the outputs are updated without waiting for a clock edge.
4-State Moore State Machine
The outputs of a Moore state machine depend only on the present state. The outputs are written only when the state changes (on the clock edge).
Safe State Machine
This example uses the syn_encoding synthesis attribute value safe to specify that the software should insert extra logic to detect an illegal state and force the state machine's transition to the reset state.
User-Encoded State Machine
This example uses the syn_encoding synthesis attribute value user to instruct the software to encode each state with the value defined in the Verilog HDL source code. By changing the values of the state constants, you can change the encoding of the state machine.
Download the files used in this example:
- Download mealy_state_machine_v.zip
- Download moore_state_machine_v.zip
- Download safe_state_machine_v.zip
- Download user_encoded_machine_v.zip
- Download Verilog HDL Template for State Machines README File
Each zip download includes the Verilog HDL file for the state machine and its top level block diagram.
The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.