# Verilog HDL: Parameterized Counter

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This example shows how to instantiate an LPM function in Verilog HDL. In this case, an LPM_COUNTER is instantiated using the aclr, clock, and q ports. The parameter values are set with the keyword defparam, as shown in red text. Both the port mapping and the parameter names are referred to by the period (.) operator after the variable name. In this case, the variable is u1.

For more information on using this example in your project, go to:

check_lpm.v

module check_lpm ( clk, reset, q);
// Port Declaration

input   clk;
input   reset;
output  [7:0] q;

lpm_counter u1 (.aclr(reset), .clock(clk), .q(q));
defparam u1.lpm_width= 8;
defparam u1.lpm_direction= "UP"

endmodule