Verilog HDL: 8x64 Shift Register with Taps

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This example describes an 8-bit wide, 64-bit long shift register with equally spaced taps in Verilog HDL. Synthesis tools detect groups of shift registers and infer altshift_taps megafunction depending on the target device architecture.

Figure 1. 8x64 shift register top-level diagram.

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Table 1 lists the ports and gives a description for each.