This design example implements a high-performance JPEG decoder using Open Computing Language (OpenCLTM). The solution consists of several OpenCL kernels connected via Intel's channels vendor extension, where each kernel performs one step in the JPEG decoding pipeline (e.g. Huffman decoding, inverse DCT).
This implementation can decode JPEG images at a rate of 2.6 MBps, which enables saturation of a PCI Express* (PCIe*) Gen2x8 link for transferring the decoded image back to the host memory.
- Single work-item kernels
- Kernel channels
- Overlapping memory transfers and kernel invocations
The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux* package includes a Makefile and the Windows* package includes a Microsoft Visual Studio 2010* project.
The following downloads are provided for this example:
- v17.1 x64 Linux* package (.tar.gz) ›
- v17.1 x64 Windows* package (.zip) ›
- JPEG Decoder Overview and Implementation (.pdf) ›
The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.
Software and Hardware Requirements
This design example requires the following tools:
- Intel® FPGA Software v17.1 or later
- Intel® FPGA SDK for OpenCL™ v17.1 or later
- On Linux*: GNU Make and gcc
- On Windows*: Microsoft Visual Studio 2010*
To download the Intel design tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Intel® FPGA SDK for OpenCL.
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.