This example demonstrates an Open Computing Language (OpenCL™) implementation of a fast Fourier transform (FFT). The example processes multiple sets of 4096 complex single-precision floating-point values. The input data is ordered and the output data is in bit-reversed order.
For demonstration purposes, this example contains a single radix-4 FFT engine capable of processing eight data points per clock cycle. Depending on the end application and the available FPGA resources, more instances of this engine can be instantiated for higher performance, subject to the memory bandwidth available on the OpenCL board.
The FFT engine is implemented as a single work-item kernel to efficiently implement a sliding window design pattern, which is used to represent delay elements. Additional details are available in the example package.
- Sliding window design pattern
- Single work-item kernel
The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux* package includes a Makefile and the Windows* package includes a Microsoft* Visual Studio 2010 project.
The following downloads are provided for this example:
The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.
Software and Hardware Requirements
This design example requires the following tools:
- Intel® FPGA software 17.1 or later
- Intel FPGA SDK for OpenCL 17.1 or later
- On Linux: GNU Make and gcc
- On Windows: Microsoft Visual Studio 2010
To download the Intel design tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Intel FPGA SDK for OpenCL.
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.