The variable integer rate decimation filter design example demonstrates how to use the Intel® DSP Builder Advanced Blockset (DSPB-AB) to implement a decimation filter that can change its decimation rate at run time. It also supports multiple channels and exploits automatic folding of DSPB-AB to generate register transfer level (RTL) code that maximizes hardware reuse for resource saving. The current design supports decimation rates of 1, 2, 4, 8, and 16. However, you can easily modify the design to support other integer decimation rates.
You can efficiently implement conventional decimation by M filters through polyphase decomposition with an input commutator and M parallel paths. Each path is a polyphase of the original prototype filter. If the input commutator skips every other phase, instead of going through all M paths, the decimation rate becomes M/2, and so on.
In the real design, instead of having a commutator and a parallel bank of finite impulse response (FIR) filter paths, we implement only one polyphase FIR filter, where the coefficients corresponding to the polyphases change every cycle at the input sample rate. It has the same effect as delivering input samples successively to a parallel bank of polyphases. We store the polyphase coefficients in memory, and use an input accumulator like the one used in a numerically controlled oscillator (NCO) to control which phase is currently being read out and sent to the FIR filter path. The step size of the phase accumulator controls how fast the system cycles through the polyphases, hence the decimation rate. The overflow signal of the accumulator indicates when the phases have been cycled through. When it asserts, a valid output sample is generated at the lower sample rate.
The architecture of the algorithm is shown in Figure 1.
The FIR filter path is a modified direct form FIR filter. The filter coefficients are from the coefficients look-up table (LUT) and change from one polyphase to another. An accumulator is attached to each of the multiplier outputs. It accumulates the outputs of all polyphases at its tap until the rollover signal indicates that all phases have been visited and an output is due. At that moment, a multiport adder adds up all accumulator outputs and generates a final decimated sample. At the same time, the accumulators clear the contents and get ready to the next accumulating cycle.
Reconfiguration of the decimation rate change is achieved by varying the accumulator phase increment or step size at run time. You can update the phase increment real time by a processor via the Avalon® Memory-Mapped (Avalon-MM) interface. When the decimation rate changes, the number of polyphases accumulated in the FIR filter path also changes. To maximize dynamic range, we can supply a reconfigurable scaling factor to the multiply-and-accumulate units and to the final adder output. You can also reconfigure this control register via a processor through the Avalon-MM interface.
This example also demonstrates how to take advantage of the folding feature of the DSPB-AB. Folding, or time-division multiplexing, automatically realizes resource sharing and hardware re-use based on user-specified system parameters. It is particularly useful in multichannel designs.
For more information on designing resampling filters in DSPB-AB, please refer to AN 623: Using the DSP Builder Advanced Blockset to Implement Resampling Filters (PDF).
Download the files used in this example:
Files in the .zip download include:
- vardecimator_rt.mdl—DSPB-AB design file for variable rate decimation filter
- setup_vardecimator_rt.m—MATLAB script to configure initialization and parameters of vardecimator_rt.mdl
- stop_vardecimator_rt.m—MATLAB script to plot variable rate decimation filter output and compare it with the input waveform
- vardecimator_rt_bare.mdl—Design file based on vardecimator_rt.mdl. Some non-synthesizable test bench blocks are removed for RTL generation