Nios® II System Architect Design

Recommended for:

  • Device: Cyclone® III

  • Quartus®: Unknown



The Nios II System Architect Design demonstrates how to design a digital picture viewer that allows you to view pictures stored in JPEG format. This design example also shows how to scroll through JPEG pictures stored in the external flash memory using the LCD touch-screen display. In addition, this design example shows how to utilize a Nios II processor, memory, video pipeline, LCD controller, and other peripherals to design and build a system capable of running application software, such as the digital picture viewer.

This design example is targeted to be used with the Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition.

Using This Design Example

This design example is based on the system constructed in the Nios II System Architect Design Tutorial (PDF).

Nios II system architect design files contain the hardware and software files required for this design example, as explained in the document.

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

This is a test

Figure 1. Nios II Architecture

Hardware Requirements

The Nios II Embedded Evaluation Kit consists of a Cyclone® III FPGA Starter Board and an LCD Multimedia High-Speed Mezzanine Card (HSMC) daughtercard.

The following Cyclone III FPGA starter board resources are required:

  • Cyclone III EP3C25F324 FPGA
  • Embedded USB-BlasterTM cable
  • 16-MB Intel P30/P33 flash memory
  • 50-MHz on-board oscillator

The following LCD daughtercard resources are required:

  • LCD touch-screen, 800x480 pixel display