Design Summary
This design demonstrates how to instantiate ALTGX or ALTLVDS separately from the Triple Speed Ethernet (TSE) MegaCore function instance.
This design instantiates TSE MegaCore without selecting the GXB or LVDS I/O. ALTGX or ALTLVDS is instantiated separately and configured to interface with the TSE physical coding sublayer (PCS) through a ten-bit interface (TBI), as shown in Figure 1.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.
Files in the download include:
- s4gx_tse_lvds.qar - Archive of TSE Design using ALTLVDS
- s4gx_tse_gxb.qar - Archive of TSE Design using ALTGX
Configure ALTGX with the Following Settings:
- Under the General tab, set protocol to Basic
- Under the General tab, set channel width to 10
- Under the General tab, set data rate to 1.25 Gbps and input clock frequency to 125 MHz
Note: Instantiate ALTGX_RECONFIG block for Stratix® IV GX and Arria® II GX devices.
For TSE to ALTGX Interface, Connect the Following Signals:
- tbi_rx_clk (TSE) to rx_clkout (ALTGX)
- tbi_rx_d[9..0] (TSE) to rx_dataout[9..0] (ALTGX)
- tbi_tx_clk (TSE) to tx_clkout (ALTGX)
- tbi_tx_d[9..0] (TSE) to tx_datain[9..0] (ALTGX)
Configure ALTLVDS RX with the Following Settings:
- Under the General tab, enable Dynamic Phase Alignment (DPA) mode
- Under the General tab, set deserializer factor to 10
- Under the Frequency/PLL settings tab, set data rate to 1.25 Gbps and input clock frequency to 125 MHz
- Under the DPA settings 1 tab, check ‘rx_divfwdclk’ output port and bypass the DPA FIFO option
For the TSE to ALTLVDS Interface, Connect the Following Signals:
- tbi_rx_clk (TSE) to rx_divfwdclk (ALTLVDS)
- tbi_rx_d[0..9] (TSE) to rx_out[9..0] (ALTLVDS)
- tbi_tx_clk (TSE) to 125MHz system clock
- tbi_tx_d[0..9] (TSE) to tx_in[9..0] (ALTLVDS)
Note: The TSE TBI data bus to LVDS data bus connection is in reverse order.
Note: For ALTGX and ALTLVDS reset sequence, please refer to the device handbook.