HiSPi (High-speed Pixel Interface) Imager Connectivity Design Example

Recommended for:

  • Device: Cyclone® V

  • Quartus®: v12.1

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Figure 1 – HiSPi design example (FPGA Blocks).

The High-Speed Pixel Interface (HiSPi) design example demonstrates the use of an Cyclone® V FPGA to capture streaming video from an Aptina HiSPi serial interface. The FPGA receives the pixel data from the imager.

The Design Example Performs the Following Functions:

  • Configures the Aptina sensor via I2C to output a video pattern over HiSPi
  • Configures the Qsys components via Avalon® Memory-mapped (Avalon-MM) bus
  • Deserializes the HiSPi signals
  • Parses the deserialized stream and extracts active video data
  • Outputs the active video data via an Avalon®-ST Video connection
  • Receives and monitors the Avalon-ST Video data, records statistics and detects any errors

Hardware Specifications:

  • Cyclone V Development Kit with a 5CGXFC7D6F31C7ES device
  • Terasic AHA-HSMC adapter board Aptina MT9M024 headboard

Software Tools Used to Implement and Run the Design:

  • Quartus® II version 12.1 software
  • Qsys system design tool
  • System Console debug tool

The Design Supports the Following HISPI Configurations:

  • HiSPi packetized mode
  • Embedded data is tolerated but discarded
  • 4 lanes and 20 bit pixels: 10 bit HiSPi word size
  • 2 lanes and 14 bit pixels: 14 bit HiSPi word size
  • 2 lanes and 12 bit pixels. 12 bit HiSPi word size
  • HiSPi clock transitions centered between HiSPi data transitions
  • HiSPi SLVS low VCM levels (SLVS power is 0.4 V)

Product Name Supported Devices Development Kits Supported Qsys compliant Quartus II Version
HiSPi Imager Connectivity Design Example Cyclone V (GX) Cyclone V GT FPGA Development Kit 12.1

Downloading the Design Example

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Download the HiSPi Design Example.