# Multi-channel Farrow Filter Design Example

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This example demonstrates how to use the Intel® FPGA DSP Builder Advanced Blockset (DSPB-AB) to implement a multi-channel sample rate conversion filter based on a Farrow structure.

Sample rate conversion has a wide range of applications such as wireless communications, medical imaging, and military applications. Instead of implementing polyphase decomposition, the Farrow resampling filter uses low-order polynomials to realize the same functionality, thus results in significant logic savings. It is particularly efficient for processing multiple channels or multiple parallel data paths, where all channels or data paths require the same set of filter coefficients.

In this example, we build a Farrow sample rate conversion filter using DSPB-AB primitive blocks. In particular, we demonstrate how to take advantage of the folding feature of the DSPB-AB. The folding feature of the DSPB-AB automatically realizes resource sharing and hardware re-use based on user-specified system parameters.

The functional block diagram of a Farrow filter is shown in Figure 1. All modules are designed using primitive blocks in DSPB-AB.

Figure 1. Farrow filter block diagram

The symbol r is used to quantify the sampling phase difference between the current input and desired output sample. The value is normalized between 0 and 1. For each output sample, you can calculate r using the following formula:

r = (Output_time – Input_time)* Input_Sampling_Frequency

In this demo, we used a recursive algorithm to calculate r for each output sample:

Formula

where n is an integer indicating the number of samples or discrete time stamp. C1 is defined as the fractional part of the inverse of rate change factor

and

## Features

This demonstration has the following features:

• Supports both decimation and interpolation.
• Supports almost any rational sample rate change factor
• Supports up to 16 channels, although you can easily modify the design to support more channels
• Supports parameterization via a setup script
• Supports easy modification of the resampling filter (polynomial) order by extending the length of the tap delay lines
• Provides initialization and post-simulation scripts to configure parameters and compare and check outputs
• Supports automatic folding, allowing time-division multiplexing on multipliers, adders, and other hardware resources

Note 1: For version 9.1, the design requires that the FPGA clock rate is an integer multiple of both the input sample rate and output sample rate. In future releases, the output sample rate does not have to divide the FPGA clock rate. Therefore, it can theoretically support irrational downsampling rate changes as well. There is no structural changes for the different sample rate it supports.

Note 2: All channels should be processed by one data path (i.e., a single wire in the DSPB-AB design). If you have a large number of channels, you should increase your FPGA clock rate such that you don’t have to split the data channels onto multiple parallel data paths. To support multiple wires or multiple data paths, you need to modify the data alignment block, which is not covered in this example.

For more information on designing resampling filters in DSPB-AB, please refer to AN 623: Using the DSP Builder Advanced Blockset to Implement Resampling Filters (PDF).