The Avalon Verification IP Suite provides bus functional models (BFMs) to simulate the behavior of various Avalon interfaces. It also provides monitors to verify Avalon protocols. This suite facilitates the verification of intellectual property (IP) that includes Avalon interfaces.
Figure 1 shows the block diagram of a verification testbench using the Avalon Verification IP Suite. You create the test system by connecting the suite components to the design under test. In the test module, you control the test flow by communicating to the Avalon Verification IP Suite components via the application programming interface (API).
This design example demonstrates how you can use Avalon Verification IP Suite to verify a design under test. As this is a simulation-based design, using this design doesn't require any Intel FPGA development kits. However, you need to have the ModelSim* simulation tool installed on your machine.