Passive Serial Configuration

Passive serial (PS) configuration can be performed using an Intel® FPGA download cable, an Intel FPGA configuration device, or an intelligent host such as a microprocessor. During PS configuration, data is transferred from a configuration device, flash memory, or other storage device to the Intel FPGA device on the DATA0 pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred at a rate of one bit per clock cycle.

For more information, please refer to the configuration chapter of the relevant Intel FPGA device in the Configuration Handbook.

Configuration Methods

  • Use a processor as an external host
  • Use a MAX® series CPLD as an external host

Embedded Solutions

Application Note

Reference Design